As the requirements for increased device performance and reliability have become more and more challenging in VLSI and ULSI silicon circuit technology, techniques to avoid contamination and processes to generate very clean wafer surfaces have become critically important.
Many cleaning operations are necessary in the course of semiconductor manufacturing and must be performed at certain critical processing steps. To ensure a fast, selective, uniform and cost effective cleaning, the Center Nanoelectronic Technologies provides a state-of-the-art cleaning platform.
As a chain link between suppliers and fab we are able to screen, evaluate and optimize new chemicals and processes from laboratory scale up to testing on own 2x nm node test wafers.
- 2x nm technology node
- From beaker test to 300 mm industry scale
- PostEtchResidualRemoval (PERR)
- Photoresist stripping
- Lithography stack rework
- Dual damascene metal hard mask etch
- Bath life time evaluation
- Consumable benchmarking